1. Field of the Invention
The present invention relates to a semiconductor device and a method for producing the semiconductor device.
2. Description of the Related Art
There has been proposed a flash memory that includes a memory cell including a floating gate and a control gate formed on a side wall of a pillar-shaped semiconductor layer, which is formed on a surface of a semiconductor substrate, so as to surround the pillar-shaped semiconductor layer. In this flash memory, the capacitance between the floating gate and the control gate can be increased with a small area occupied on the substrate, and the flash memory has high writing and erasing efficiencies (e.g., refer to Japanese Unexamined Patent Application Publication No. 8-148587).
In such a structure in which the floating gate surrounds the pillar-shaped semiconductor layer, the control gate surrounds the floating gate. Therefore, the width of control gate lines increases and the distance between the control gate lines decreases when a memory cell array is formed, which increases the capacitance between the control gate lines. On the other hand, if the distance between the control gate lines is increased, the degree of integration decreases.
In order to increase the capacitance between the floating gate and the control gate, there has been proposed a tri-control gate surrounding gate transistor (TCG-SGT) flash memory cell (e.g., refer to Takuya Ohba, Hiroki Nakamura, Hiroshi Sakuraba, Fujio Masuoka, “A novel tri-control gate surrounding gate transistor (TCG-SGT) nonvolatile memory cell for flash memory”, Solid-State Electronics, Vol. 50, No. 6, pp. 924-928, June 2006).
The TCG-SGT flash memory cell has a structure in which the control gate covers not only side surfaces but also an upper surface and a lower surface of the floating gate. Therefore, the capacitance between the floating gate and the control gate can be increased, whereby writing and erasing are easily conducted. However, such a structure in which the control gate covers the upper surface and lower surface of the floating gate is not easily produced.
In order to decrease the parasitic capacitance between a gate line and a substrate, a first insulating film is used in known MOS transistors. For example, in a FinFET (e.g., refer to High performance 22/20 nm FinFET CMOS devices with advanced high-K/metal gate scheme, IEDM2010, CC. Wu, et. al, 27.1.1-27.1.4.), a first insulating film formed around a fin-shaped semiconductor layer is etched back to expose the fin-shaped semiconductor layer, whereby the parasitic capacitance between the gate line and the substrate is decreased.
In order to decrease the parasitic capacitance between the gate line and the substrate, it is also effective in SGT (surrounding gate transistor) flash memory cells to use such a first insulating film. However, in SGT flash memory cells, some improvement for forming the pillar-shaped semiconductor layer, in addition to the fin-shaped semiconductor layer, is required.